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Altera_Forum
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10 years ago

LE and memory blocks in a cyclone

Hello, I'm quite new in the world of the FPGA, indeed, I'm an engineer student in end-of-studies internship which is about using a FPGA. Well, I'm telling you that because I guess that you wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Do you mean efficiency or utilisation?

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Well, actually I don't really know. To build my architecture, I just utilize 3 IP using the megawizard of Quartus and a top level to link them together.

So, I guess Altera's IP use the memory efficiently.

And the problem is that in my poor little test, I use 500K of the 600K memory bit of my cyclone IV, so do you think I can optimize it?