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Honored ContributorJTAG target board circuit design
Hello,
Im trying to program an epm7064s fpga jlead package device. I am using the USB blaster which is integrated into the terrasic micro max II development board. I am using a PLCC socket with 44 pins which I wirewrapped the TCK, TDO, TDI and TMS pins and connected them with short wires (aprx 3 inches) to the header connector which connects to the header on the micro max II development board. I've attached the pullup and pulldown (TCK) resistors and VCC directly to the header connector. Its not pretty, but I thought this dirrect route should provide clean signals. I also applied 5V (decoupled) and GND to all of the VCC and GND pins on the FPGA, and also applied VCC to all of the IOs. All the connections other than the JTAG lines were done on strip board with holes for the JTAG lines to pass through (very tedious). Needless to say, it didnt work. I've been using Quartus II and I keep getting the following message: Info: Started Programmer operation at Fri Oct 28 17:16:03 2011 Info: Unrecognized device Error: JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device Error: Operation failed Info: Ended Programmer operation at Fri Oct 28 17:16:03 2011 Before I break down and actually have a PCB made, I would like to know if I am doing something wrong, which I would need to clarify before designing the PCB anyways. The following are my specific concerns: -should TCK be pulled down with a 1K resistor and is 5% tolerance acceptable? (Altera application brief 145 says to pull up TCK with a 10K resistor when using the bitblaster cable) -should TMS and TDI be pulled up with 10K resistors? (I get conflicting info about this, some documents say to pull up with a 1K resistor) -should TDO not be pulled up or down? (I found one document that suggests using a low value resistor in series with the TDO line) -should VCC and GND be applied to the corresponding pins on the FPGA? -should all IOs have VCC applied to them? -what is an acceptable decoupling cap value for this application? I've researched this topic extensively but haven't got any specific information that would relate to my application (USB blaster to program an Altera 7000s device). I've tried to fill in the blanks and attempted to program the FPGA with different configurations. I sure would appreciate any answers to the previous questions and/or advice on how to go about troubleshooting this problem. Thank you for any feedback, Chuck4 Replies
Altera_Forumleon_heller,
Thank you for the circuit diagram, I definitely haven't tried this configuration. I've used slightly different values on the pull ups and pull downs and I certainly didn't connect a clock to any of the clock inputs (the major discrepancy I suspect). I see that circuit was for the epm570 but it sounds like you have used the same circuit for the max7000. I will give this a try. Thanks a bunch, Chuck- Altera_Forum
I've never had any problems with JTAG connections like this to MAX7000 devices:
http://www.leonheller.com/cpld/proto(page1).pdf (http://www.leonheller.com/cpld/proto(page1).pdf) - Altera_Forum
thepancake,
Thanks for the reply. I will take a look at the schematic review worksheets. Too bad there isn't one specifically for the max7000 family. The application note that I referred to (app. brief 145) was specifically for the max7000 and said to pull up the TCK but that was when using the Bitblaster cable, so maybe it operates differently than the USBblaster. I did find some documentation that expressed how sensitive the TCK is to reflections. If this is the case, maybe a socket type chip can't be programmed with the USBblaster cable. chuck - Altera_Forum
i've been using the Schematic Review Worksheets as a golden reference for this kind of information. there isn't one for the MAX parts, but i've used Stratix IV and Cyclone IV worksheets
http://www.altera.com/download/board-layout-test/schematic-review-ws/srw-index.jsp -TCK pull down 1k, i'm sure 5% is fine -TMS and TDI 10k pull up -TDO has neither pull up or pull down (because the device drives it) -yes, you should connect all power pins, don't forget about the e-pad underneath newer QFP -not sure on the decoupling for your application
