Hello, I would like to interface Cyclone IV JTAG interface via both ways : 1. JTAG USB blaster. 2. FTDI FT2232 MPSSE interface. I am using VCCIO 3.3V in Jtag bank and in figure 8-23 in cyclone IV handbook its says to connect JTAG voltages TDIpullup,TMSpullup and PIN4 JTAG connector to VCCA = 2.5v. It says that--- ""All I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 . You must power up the VCC of the download cable with a 2.5-V supply from VCCA" My problem is when interfacing Cyclone via FT2232. ft2232 has 3.3v I/Os. Will it be safe???

--- Quote Start --- I would like to interface Cyclone IV JTAG interface via both ways : 1. JTAG USB blaster. 2. FTDI FT2232 MPSSE interface. --- Quote End --- Do you understand how to implement this? The USB-Blaster uses a parallel interface for communication between the FT245 and a MAX CPLD. The MAX CPLD interprets bytes over the cable, and then manipulates the JTAG pins on another FPGA. Are you planning on making your Cyclone IV FPGA act as a USB-Blaster? The MPSSE mode can just be tied to the JTAG pins on the Cyclone IV. The Arrow BeMicro board essentially follows this scheme. --- Quote Start --- I am using VCCIO 3.3V in Jtag bank and in figure 8-23 in cyclone IV handbook its says to connect JTAG voltages TDIpullup,TMSpullup and PIN4 JTAG connector to VCCA = 2.5v. It says that--- ""All I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 . You must power up the VCC of the download cable with a 2.5-V supply from VCCA" My problem is when interfacing Cyclone via FT2232. ft2232 has 3.3v I/Os. Will it be safe??? --- Quote End --- The figure shows a direct connection from the programmer to the FPGA pins, so the description is being conservative (note the comment regarding third party programmers). Personally, I would buffer the TMS/TCK/TDI signals from the header using TinyLogic buffers, and buffer the TDO output to the cable with another TinyLogic buffer. The header power pin can then 3.3V, and the TinyLogic TMS/TCK/TDI buffers can be driven from your VCCIO voltage, and the TDO buffer driven by 3.3V. If your VCCIO bank voltage is lower than 2.5V, then use a dual-power rail buffer (TI and Fairchild both have devices). In this scheme, you are isolating your expensive and hard-to-rework FPGA from your USB-Blaster cable or cheap knock-off cable. If something goes wrong, and you blow a TinyLogic buffer, they are easy to replace. Cheers, Dave

Hello Dave, I think I will add in the TinyLogic buffers into my design after reading your post, as I did read that the JTAG pins are not clamped. However, I am planning on powering up my EP4CE115 484FBGA bank 1 with VCCIO = 3.3V, where bank 1 contains the JTAG pins. I have 2 questions. If I setup my connections as I have done in the jpeg that I have attached will: USB-Blaster Jtag programmer power up correctly? The signals from the USB-Blaster program the FPGA correctly? Regards, Michael Woods

--- Quote Start --- If I setup my connections as I have done in the jpeg that I have attached will: USB-Blaster Jtag programmer power up correctly? The signals from the USB-Blaster program the FPGA correctly? --- Quote End --- Your pin 8 is wrong. Look at the USB-Blaster user guide, page 18 and in Table 2-2 on p20 http://www.altera.com/literature/ug/ug_usb_blstr.pdf Pin 8 in your schematic should be a no connect. You should really re-number your schematic symbol to use the standard pin numbering convention of odd down one side and even down the other. Note that this is how the pin numbers are shown in Table 2-2 of the user guide. You have mapped them correctly in your schematic (with the exception of pin 8), but it could be confusing for users of your design. The FPGA will tri-state TDO, so it will float. Add a pull-up to TDO so that the input to the USB-Blaster is always at a valid logic level. Cheers, Dave

Hello Dave, So with the pin 8 line being left floating on the board and with appropriate buffering and pulling TDO line high with say a 10K resistor I should have a working programming interface between FPGA and USB-Blaster? Regards, Michael

--- Quote Start --- So with the pin 8 line being left floating on the board and with appropriate buffering and pulling TDO line high with say a 10K resistor I should have a working programming interface between FPGA and USB-Blaster? --- Quote End --- Yes. If you are going to the trouble of buffering the inputs, then also buffer the TDO output, or at least put a 100-ohm series resistor in the path to provide some form of ESD protection (the TDO trace would go from the FPGA, to the pull-up, then through the series resistor to the JTAG connector). Why go to this trouble? Well, the JTAG connector is the one place a user can get their electrostatically charged fingers! Cheers, Dave

JTAG interface | Altera Community

15 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

One last question, what is the maximum frequency signal that you can pass through the TinyLogic buffers? Because I intend on passing through a signal that operates at about 25MHz.

--- Quote End ---

I've used them at 125MHz, so 25MHz is fine.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hello Dave,

I think I may try the TinyLogic buffers, because I could place them where ever I need them. Which would allow me to reduce unused space on my board as this is the number 1 priority in my design.

I get my pcbs assembled in china and they order in from many places so regional availability is not a problem.

One last question, what is the maximum frequency signal that you can pass through the TinyLogic buffers? Because I intend on passing through a signal that operates at about 25MHz.

Regards,
Michael
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Upon reading your comment, I believe that I will be using instead the SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS, and have it always enabled with a weak pull up or pull down resistor to set the value. Will this change enable me to drive the JTAG lines correctly?

--- Quote End ---
This part will be fine.

I'm not sure where you are located, but if you can buy components in the US, the pricing on Mouser for the SN74LVC244A is $0.55 each

http://www.mouser.com/productdetail/texas-instruments/sn74lvc244ansr/?qs=sgaepimzzmuiiwkaiwck2vxqsqozkdecnc%252bi5rnfnoq%3d

whereas the TinyLogic device 512-NC7WZ16P6X is $0.14

http://www.mouser.com/productdetail/fairchild-semiconductor/nc7wz16p6x/?qs=sgaepimzzmuiiwkaiwck2y9zx6ozihaoqc8dih16pqg%3d

I find PCB layout much cleaner using smaller buffers, since you can place them where you need them (and have nice traces).

The 'classic' 244 buffers may be easier to source in other areas of the world though. I just wanted to point out that the smaller parts are not pricey.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hey Frank,

--- Quote Start ---
It's unable to drive the JTAG signals without adding strong (e.g. 470 ohm) pull-up resistors. Not a good idea at all.
--- Quote End ---

Good point. Thanks for correcting me.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

For the resistor I may use a 22ohm resistor, as I have one already in my design, but what would be the effect on the TCK line, if the resistance is not right, because I dont want to have to rework the PCB once it is made.

I will only be using the one FPGA device in my design.

--- Quote End ---
22-Ohms will be fine.

The key thing is that you have a resistor footprint on the PCB. That way if you do see ringing on the TCK line, you can adjust its value without a re-spin of the PCB.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hello FvM,

Upon reading your comment, I believe that I will be using instead the SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS, and have it always enabled with a weak pull up or pull down resistor to set the value. Will this change enable me to drive the JTAG lines correctly?

Regards,
Michael
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Is there anything wrong with me using the open drain buffer?
--- Quote End ---

It's unable to drive the JTAG signals without adding strong (e.g. 470 ohm) pull-up resistors. Not a good idea at all.
Altera_Forum
Honored Contributor
14 years ago
Hello Dave,

--- Quote Start ---

What is the price, and layout difference between this and a couple of TinyLogic devices? (Which have input voltage tolerance of up to 7V)

--- Quote End ---

The package that I am using for my design is a 2.5x3mm QFN package, and costs about 0.89USD per component, as I am only going to make a few of them bulk price is not an option.
The input tolerance is 5.5V, but the datasheet states 6.5V maximum limiting value, so it should be ok.

--- Quote Start ---
Now add a 30-ohm series resistor to your TCK output. This is a source termination that you can adjust to eliminate any ringing on the clock signal.

I assume that TCK and TMS are only going to a single FPGA load? If they are not, then you can put dual-source terminations on the buffer outputs and drive them to two loads.
--- Quote End ---

For the resistor I may use a 22ohm resistor, as I have one already in my design, but what would be the effect on the TCK line, if the resistance is not right, because I dont want to have to rework the PCB once it is made.

I will only be using the one FPGA device in my design.

Regards,
Michael
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I have altered my design to use a 74LVC07A, as in the jpeg. Is there anything wrong with me using the open drain buffer?

--- Quote End ---
No there is nothing wrong with using the open-drain buffer.

What is the price, and layout difference between this and a couple of TinyLogic devices? (Which have input voltage tolerance of up to 7V)

http://www.fairchildsemi.com/ds/nc/nc7wz16.pdf

--- Quote Start ---

The schematic is a bit messy, but I have linked the TDO output through the hex buffer.

--- Quote End ---
That's good.

Now add a 30-ohm series resistor to your TCK output. This is a source termination that you can adjust to eliminate any ringing on the clock signal.

I assume that TCK and TMS are only going to a single FPGA load? If they are not, then you can put dual-source terminations on the buffer outputs and drive them to two loads.

Look at this schematic for even crazier examples ...

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hello Dave,

I have altered my design to use a 74LVC07A, as in the jpeg. Is there anything wrong with me using the open drain buffer?

The schematic is a bit messy, but I have linked the TDO output through the hex buffer.

Regards,
Michael

Forum Discussion

JTAG interface

15 Replies

Recent Discussions

Preconfiguration BSDL Editor for Agilex 7 with disabled F-Tiles

Fail to enumerate RTile PCIe in the AVSTx8 configuration

Agilex 5 HPS EMIF - Differential Pair Polarity Inversion Support

Boundary scan access to SDM pins on Agilex 7

vertical side marking on MAX10 UBGA169 package?