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Honored Contributor
Honored ContributorJTAG interface
Hello, I would like to interface Cyclone IV JTAG interface via both ways : 1. JTAG USB blaster. 2. FTDI FT2232 MPSSE interface. I am using VCCIO 3.3V in Jtag bank and in figure 8-23 in c...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have altered my design to use a 74LVC07A, as in the jpeg. Is there anything wrong with me using the open drain buffer? --- Quote End --- No there is nothing wrong with using the open-drain buffer. What is the price, and layout difference between this and a couple of TinyLogic devices? (Which have input voltage tolerance of up to 7V) http://www.fairchildsemi.com/ds/nc/nc7wz16.pdf --- Quote Start --- The schematic is a bit messy, but I have linked the TDO output through the hex buffer. --- Quote End --- That's good. Now add a 30-ohm series resistor to your TCK output. This is a source termination that you can adjust to eliminate any ringing on the clock signal. I assume that TCK and TMS are only going to a single FPGA load? If they are not, then you can put dual-source terminations on the buffer outputs and drive them to two loads. Look at this schematic for even crazier examples ... http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf) Cheers, Dave
