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Honored Contributor
Honored ContributorJTAG interface
Hello, I would like to interface Cyclone IV JTAG interface via both ways : 1. JTAG USB blaster. 2. FTDI FT2232 MPSSE interface. I am using VCCIO 3.3V in Jtag bank and in figure 8-23 in c...
Altera_ForumHonored Contributor
Honored ContributorHello Dave,
--- Quote Start --- What is the price, and layout difference between this and a couple of TinyLogic devices? (Which have input voltage tolerance of up to 7V) --- Quote End --- The package that I am using for my design is a 2.5x3mm QFN package, and costs about 0.89USD per component, as I am only going to make a few of them bulk price is not an option. The input tolerance is 5.5V, but the datasheet states 6.5V maximum limiting value, so it should be ok. --- Quote Start --- Now add a 30-ohm series resistor to your TCK output. This is a source termination that you can adjust to eliminate any ringing on the clock signal. I assume that TCK and TMS are only going to a single FPGA load? If they are not, then you can put dual-source terminations on the buffer outputs and drive them to two loads. --- Quote End --- For the resistor I may use a 22ohm resistor, as I have one already in my design, but what would be the effect on the TCK line, if the resistance is not right, because I dont want to have to rework the PCB once it is made. I will only be using the one FPGA device in my design. Regards, Michael
