JTAG and/or IO pin usage

You can connect the pin which drives the JTAG pins to other IO if you're careful, but you can't reuse the pins themselves.

The safest way is to share TCK with another clock, and tie TMS high when not in JTAG mode. The MAX will then ignore TDI and tristate TDO.

An alternative is to tie TCK either high or low, while using other pins as IO. The MAX will ignore TDI and will probably tristate TDO, but if you get noise on TCK then it could get into a state where it drives TDO.

Hi wombat & FvM,

Thanks for the replies. If JTAG can't be reenabled easily I won't bother disabling it.

Ok, I'll try with GCLRn & TCK tied together; so whenever I want to reset my CPLD I'll pull TMS high and clock TCK until the TAP's in test-logic-reset and the all my registers have been cleared. The I presumably have TMS/TDI/TDO available for inputs? I might connect TMS/TDI/TDO to some other IO points initially in case they're not available.

Thanks again,

Regards,

Doug.

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The basic question is: is it possible to program a EPM3064 through the JTAG pins, then use the JTAG pins as IO, then later reprogram it?

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Look at the pinout for the device;

http://www.altera.com/literature/dp/max3k/epm3064a.pdf

The JTAG pins are dedicated pins that cannot be used as I/O afterwards.

If you want to reuse the JTAG header on the board to access I/O pins on the FPGA, then that is definitely possible; see page 8 of the attached schematic for an example. In this scheme, a 2-pin header is either attached or removed to route the signals to JTAG pins or to I/O pins.

Back when you could interface to JTAG using the parallel port, I used to use an unused pin on the ByteBlaster cable to select the operating mode (via the HDR_JTAG_SEL signal), however, the newer USB-Blaster cables cannot easily be re-tasked as a general purpose digital I/O interface (though I'll figure it out one of these days ...). Make sure the resistor on the HDR_JTAG_SEL signal is a no-mount, as it seems to confuse the USB-Blaster.

Cheers,

Dave

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http://www.altera.com/literature/dp/max3k/epm3064a.pdf

The JTAG pins are dedicated pins that cannot be used as I/O afterwards.

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Oops, my bad, I didn't read note (1) :)

It looks like you can use them as I/O. But perhaps as FvM suggests, its only if you disable JTAG. In that case, you can use the scheme I mentioned.

Cheers,

Dave

Thanks Dave for the notes.

That's a little confusing for me (note 1 in the altera doc, I can only guess that 'configured for isp' means entering the programming mode). I'll just treat the JTAG port as if it's always a JTAG port then, and double-up the JTAG connections to spare IO (which I have heaps of) and be done with it - easy!

PS, no I don't want to reuse the header - in fact I want to get rid of the header & connect some uC IO to the CPLD with the same uC IO doing JTAG-y stuff as well as mode selection for my user code.

I think I'm sorted now though.

Cheers,

Doug.

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I'll just treat the JTAG port as if it's always a JTAG port then

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That is generally the best way to do things.

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I want to get rid of the header & connect some uC IO to the CPLD with the same uC IO doing JTAG-y stuff as well as mode selection for my user code.

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In that case, check out the JTAG-y stuff in this schematic:

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)

Why are you thinking of using this particular CPLD?

The MAX II devices are much nicer, eg., EPM570 in a TQFP 100 package. When I want a little glue logic, I find that one quite handy. The schematic I just referenced to uses a couple of them.

Cheers,

Dave

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That is generally the best way to do things.

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Great!

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Why are you thinking of using this particular CPLD?

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1) I need the 5V-tolerant inputs

2) because it's still pretty cheap (I was originally looking at the epm3032 which is very cheap, but alas too small)

Cheers,

Doug

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1) I need the 5V-tolerant inputs

2) because it's still pretty cheap (I was originally looking at the epm3032 which is very cheap, but alas too small)

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Fair enough. I'd place-and-route your CPLD design before making any final decision (since the part is a logic cell light-weight). If you need more logic, then you can use bus-switches to get 5V tolerance. The schematic I referenced has a 5V tolerant, hot-swappable, compactPCI interface.

Cheers,

Dave

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I'll just treat the JTAG port as if it's always a JTAG port then, and double-up the JTAG connections to spare IO (which I have heaps of) and be done with it - easy!

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???

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If JTAG can't be reenabled easily I won't bother disabling it.

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Unselect the "Enable JTAG BST support" option in "Device and Pin Options/General Tab". Then the four JTAG pins are available for assignment as general I/O.

I agree, that the description of this feature in the device hardware manual isn't particularly clear. I didn't try it yet, but it's obvious to me, that the JTAG functionality can't be re-enabled with standard low voltage levels, otherwise the usability of the respective I/O pins would be restricted.