Issue with MAX10 FPGA ADC
We appear to have an issue with the ADC on the MAX 10 ADC. The ADC inputs appear to be feeding current onto the signal being measured. We are using the ADC to measure the voltage of a number of potential dividers. In the first example we would expect to to see 300 mV at the ADC input but using a DVM we measure 330 mV. This is confirmed by interrogating the ADC. This is the case across all 8 inputs. It seems that the ADC inputs are feeding about 130 uA back onto its inputs.
The only way I can explain this is that the weak internal pull-ups appear to be enabled. According to the MAX 10 documentation they can have a value of between 7 and 34 kOhms. A value of around 13k would give the effect we are observing.
If we define the pins as GPIO and turn off the internal pull-ups the problem is resolved.
It appears that once the pins are defined as ADC inputs it is not possible to turn on or off the internal pull-ups but they default to being enable. Are we mistaken?
We are currently using Quartus Prime 18.1. The device we are using is: 10M08SAU169A7G.