Issue with Cyclone 10 LP PLL
Hi there,
I am working in a bring-up of a board that contains a Cyclone 10 LP FPGA.
I am trying to use the 2x PLLs that the FPGA contains.
I have generated from the 100MHz input clock, 2x 200KHz using ALTPLL IP.
But, I see that the "locked" out signal goes from "1" to "0" after programming the sof and that the output frequency us around 170KHz instead of the 200KHz.
I have tried different compesation modes and made tests with different frequencies, but I always get the same behavior, "locked" signal does not get stable in "1" and the PLL output frequency is always below the target (i.e. 15MHz I get 12MHz, 5MHz I get 4Mhz, ...)
I am unsure if it's IP config problem or something else, like HW isuse.
A small capture of the IP:
How can I proceed?
Thanks