Forum Discussion
imuguruza
New Contributor
New ContributorIssue with Cyclone 10 LP PLL
Hi there, I am working in a bring-up of a board that contains a Cyclone 10 LP FPGA. I am trying to use the 2x PLLs that the FPGA contains. I have generated from the 100MHz input clock, 2x 200KHz u...
AqidAyman_Altera
Regular Contributor
Regular ContributorMay I know if you confirm the 100MHz input clock is stable through waveform measurement? Another thing to highlight here is the power supply for analog, VCCA. Does it confirm supplying the stable power? The VCC must rise monotonically.
Refer to the datasheet for the VCCA recommended operating condition:
Regards,
Aqid
