Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is there any "side effect" when using GPIO in DE2-115 to receive 48MHz CLKIN ?

Hi,

I went through the schematic of DE2-115, and i can be sure that, all of the GPIO pins connected to Bank 4 of FPGA chip does not support CLOCKIN function.

The full compilation was not successful when i specified the clock source of a PLL(with ratio 1:1) coming from a GPIO, but if i do not use a PLL, the full compilation was successful, and the design seems to work well too. (Full compilation was successful, maybe Quartus 2 have no idea i am using GPIO to receive high frequency clock?)

So, i am wondering is there any "side effect" when using GPIO in DE2-115 to receive 48MHz CLKIN ?

Thank You.:)

Regards,

Michael

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The primary side effect as you mentioned is the inability to effectively use a pll off that clock. However you can still use it as a clock signal, it just may have some extra input delay due to the fact it doesn't have the dedicated routing resources to the global clock lines.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    So.. you don't think there will be some kinda signal interference to other pins nearby caused by the high frequency signal due to mutual inductance? i am just guessing, since i am inputting high frequency clock signal through a pin that is not dedicated for this purpose.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    There are restrictions on max toggle rates, depending on I/O standard and other. But they are far above 48 MHz.

    There are also restrictions for having single ended pins next to differential pins, which also don't apply to your case.

    However, that has nothing to do with the error you're getting.

    As anakha wrote, Quartus will simply not feed a PLL from a general purpose pin. Nor will it feed a global clock network, with means your design is running with large clock skew.

    If you run into problems with that, the best solution will be to feed the clock to a dedicated clock pin (the DE2 and DE2-70 boards had a SMA connector for external clock).

    Bar that, you can just pass the clock signal though a LCELL primitive, since Quartus will feed the LCELL's output to either a global clock network or a PLL.