Is there any "side effect" when using GPIO in DE2-115 to receive 48MHz CLKIN ?

There are restrictions on max toggle rates, depending on I/O standard and other. But they are far above 48 MHz.

There are also restrictions for having single ended pins next to differential pins, which also don't apply to your case.

However, that has nothing to do with the error you're getting.

As anakha wrote, Quartus will simply not feed a PLL from a general purpose pin. Nor will it feed a global clock network, with means your design is running with large clock skew.

If you run into problems with that, the best solution will be to feed the clock to a dedicated clock pin (the DE2 and DE2-70 boards had a SMA connector for external clock).

Bar that, you can just pass the clock signal though a LCELL primitive, since Quartus will feed the LCELL's output to either a global clock network or a PLL.