Honored ContributorHi,
We are looking for a FPGA solution which can be used for replacing the DRAM and connect a FPGA board to a dimm slot directly. The DRAM should be on the FPGA board. What we want to do is to intercept the traffic between a physical machine and the DRAM using the FPGA board? Any suggestion is highly appreciated! Best, Kai
Honored ContributorDo you want to sniff the traffic or do you plan to have the FPGA between the slot and the memory (with the traffic flowing through the FPGA)?
Also, what flavor of SDRAM (DDR2/3/4) and how fast?Honored ContributorThe FPGA should locate between the slot and the memory to intercept and encrypt/decrypt the data.
DDR3 is preferred, and DDR2/4 should also work. About the speed, as far as it can support OS booting and running, it should be fine for now! Thanks!
New ContributorHello,
With technological advancements of FPGA and the availability SDRAM Controller IPs, I guess the answer to this question should be revisited.
Kind regards,
Olivier
Honored ContributorNo matter how fast you run the FPGA you would be injecting a lot of latency between the system memory controller and the memory. How can you make that work, especially for reads? I hate to be a hater, but I don't think it's possible.
Honored ContributorSo you mean that if a FPGA locates between the system memory controller and the memory, the performance will be too bad to run any OS on it? I'm new to this area, please let me know if my proposed solution doesn't make sense. Thanks.
Honored ContributorSDRAM interfaces are fast, and the interface timing is fixed for a given memory. Some interfaces allow insertion of wait states to slow things down, but SDRAM is not one of those interfaces. It's just not possible to do what you want with a standard memory controller that is not aware of the delay added by the FPGA. You would be better off doing the encryption and decryption in software.
Honored ContributorThanks! Now it's quite clear to me.
Honored ContributorAs others have said this isn't possible. Even if it were, it would be a bad idea to impose delay between a processor and its memory system. You should analyze your system requirements to determine the best way to interconnect. PCI and PCI express are common, but I2C, SPI, RapidIO have also been used.
