Is it feasible to use the GPIO of Cyclone IV to generate a 148.5MHz clock signal?

The Cyclone IV PLL's have dedicated PLL output pins that should be used in this case for the best jitter and timing performance.

Is 148.5 MHz output reasonable with these, yes, but it depends on the IO standard used. I remember the old altera handbooks having a Fmax specification for each IO standard, but I don't see it in the handbook anymore. It may be they removed it, because it's too dependent on the loading and the IO option used, and people were complaining.. I don't know.

LVDS standards can do 600-800 MHz toggling with not too much difficulty.

Pete

Hi Pete (anakha),

Thank you for your reply!

Yes, I did find the IO speed specification of Cyclone II in cyclone ii handbook, while such a specification is absent for Cyclone IV in cyclone iv handbook. That's why I tried to post this thread. And yet I don't think there would be any difficult for a 45nm-Cyclone to generate a 148.5MHz external clock output.

Actually, I am trying to verify my design by using a Cyclone II Evaluation Module these days first. And we may get a Cyclone IV EVM in a few days.

Again, thank you for your help!

Naroah

Feb/22/2014

Oh, One more thing.

How can I set your thread as a "Verified Answer" or rate your post? I am new to this Altera Forum; and I don't know if I should close or delete my thread after being answered.

The thread can stay as it is, for future reference (yes, some people do search the forum before asking something ;) )

AFAIK there isn't any official way of showing a thread has been answered.

As for the rating, there used to be a reputation system on the forum, but it was disabled a while ago. It's not really used any more.

I am having a similar question.

Think about these 2 designs in which we would want to output a 200Mhz clock from a cyclone IV fpga. Let's assume a 1V5 single ended output.

Design 1: feed input clock of 200Mhz to PLL and use the dedicated output pins of the PLL for the output clock.

Design 2: feed input clock of 200Mhz to pll and use the pll to generate and internal 400Mhz clock. Use this 400Mhz clock to output a 200Mhz clock. Something like the code below might be used:

process (clk_400Mhz) begin

if( rising_edge(clk_400Mhz)) then

outputClk200Mhz_signal<= not outputClk200Mhz_signal;

end if;

outputClkPin <= outputClk200Mhz_signal;

end process;

The outputClkPin can basically be on any pin now.

Now, if we compile design 1 in Quartus, we get the following critical warning:

Critical Warning (176584): Output pin "outputClkPin" (external output clock of PLL uses I/O standard 1.5 V, has current strength 8mA, output load 0pF, and output clock frequency of 200 MHz, but target device can support only maximum output clock frequency of 170 MHz for this combination of I/O standard, current strength and load

When we compile design 2, no errors/warnings are raised! Please not that the same I/O standard and current strength is used.

Why do we get no warning? What is the real limitation? Is the 170Mhz really the max output frequency?