Is it feasible to use the GPIO of Cyclone IV to generate a 148.5MHz clock signal?

I am having a similar question.

Think about these 2 designs in which we would want to output a 200Mhz clock from a cyclone IV fpga. Let's assume a 1V5 single ended output.

Design 1: feed input clock of 200Mhz to PLL and use the dedicated output pins of the PLL for the output clock.

Design 2: feed input clock of 200Mhz to pll and use the pll to generate and internal 400Mhz clock. Use this 400Mhz clock to output a 200Mhz clock. Something like the code below might be used:

process (clk_400Mhz) begin

if( rising_edge(clk_400Mhz)) then

outputClk200Mhz_signal<= not outputClk200Mhz_signal;

end if;

outputClkPin <= outputClk200Mhz_signal;

end process;

The outputClkPin can basically be on any pin now.

Now, if we compile design 1 in Quartus, we get the following critical warning:

Critical Warning (176584): Output pin "outputClkPin" (external output clock of PLL uses I/O standard 1.5 V, has current strength 8mA, output load 0pF, and output clock frequency of 200 MHz, but target device can support only maximum output clock frequency of 170 MHz for this combination of I/O standard, current strength and load

When we compile design 2, no errors/warnings are raised! Please not that the same I/O standard and current strength is used.

Why do we get no warning? What is the real limitation? Is the 170Mhz really the max output frequency?