Is it feasible to use the GPIO of Cyclone IV to generate a 148.5MHz clock signal?

The Cyclone IV PLL's have dedicated PLL output pins that should be used in this case for the best jitter and timing performance.

Is 148.5 MHz output reasonable with these, yes, but it depends on the IO standard used. I remember the old altera handbooks having a Fmax specification for each IO standard, but I don't see it in the handbook anymore. It may be they removed it, because it's too dependent on the loading and the IO option used, and people were complaining.. I don't know.

LVDS standards can do 600-800 MHz toggling with not too much difficulty.

Pete