Honored ContributorIs it common to run SDRAM, SRAM and other memory controllers at a higher frequency than the main design, perhaps that is not integer multiple of the system frequency? This shall require use of clock crossing FIFO.
Honored ContributorNot always, though SDRAM controllers often need their own PLLs, especially if they are connected to DDR. It may not be practical to run the system clock from this PLL. But Ive seen systems where there SRAM was run at the system clock frequency, others where the memory clock domain was the same speed as the system clock, but for reasons of architecture, were asynchronous clocks.
If you have several data sources all connected to the same ram, you may need to run at a different clock speed for reasons of bandwidth. But its all a question of system design.Honored ContributorThis implies that the SDRAM is infact asynchronous to the rest of the system. Doesn't it send its data synchronized to the system clock? I am talking about the at the input interface of the memory controller.
Honored ContributorUsually, the memory controller will have an interface that is synchronised to the system clock, with internal clocks set up as you need (for bandwidth considerations etc). Clock synchronisation will be done inside the core.
