Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributoris it common to run memory interface at a higher speed than the design?
Is it common to run SDRAM, SRAM and other memory controllers at a higher frequency than the main design, perhaps that is not integer multiple of the system frequency? This shall require use of clock ...
Altera_ForumHonored Contributor
Honored ContributorUsually, the memory controller will have an interface that is synchronised to the system clock, with internal clocks set up as you need (for bandwidth considerations etc). Clock synchronisation will be done inside the core.
