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Altera_Forum
Honored Contributor
Honored Contributoris it common to run memory interface at a higher speed than the design?
Is it common to run SDRAM, SRAM and other memory controllers at a higher frequency than the main design, perhaps that is not integer multiple of the system frequency? This shall require use of clock ...
Altera_ForumHonored Contributor
Honored ContributorThis implies that the SDRAM is infact asynchronous to the rest of the system. Doesn't it send its data synchronized to the system clock? I am talking about the at the input interface of the memory controller.
