Honored ContributorHi,
Does altera have an attribute thay you can set in your vhdl code that will stop someone viewing the RTL and Technology views. I know Xilinx has a few attribute that can be set, that hides all, but does Altera? Bob
Honored ContributorIt won't help at the technology map level, but you can at least protect your IP at the RTL level by providing a .vqm file instead of a VHDL file. Run Analysis & Synthesis. Then run "Processing --> Start --> Start VQM Writer".
Honored ContributorI believe the .vqm writer is being discontinued for newer families, so that won't be an option going forward. It's also pretty susceptible to reverse-engineering since it's a structural verilog(you could argue everything is, depending how much time they want to put into it).
Another option is to export your design as a partition. The user could just import that into their design. It's a little more "strict" on how it needs to be hooked up since it won't go through synthesis again, but the .qxp file is a binary that stores information in the langauge of Quartus's database, not a known format like verilog. They both have their pros and cons.Honored ContributorThe OP was asking how to hide the info from the Technology viewer. Does the partition .qxp method actually make the Technology view inactive?
How does Altera protect their own IP from being visible in the technology view?Honored ContributorWhat? You wanted me to answer the question? : )
You're right, it won't help with that, although if you're trying to hide the technology map viewer, you're probably just as interested, if not more, in hiding the source. So the .qxp helps with that, but I'm sure it's still visible in the technology map viewer. (Note that, since the viewer is purely graphical, you're relying on someone redrawing and reverse-engineering the entire thing. If it's a few thousand logic cells, I imagine that would take a few weeks. I've done schematic conversions by hand, which is much easier, and it takes a LONG time, assuming you don't go crazy first. A simple schematic page can take 2 hours on average, so a twenty page schematic takes a week. That's not fully taking into account the typos, unhooked wires, etc. that need to be debugged. But in the end, it's do-able. Altera does provide way for vendors to protect their IP, although I don't believe it's in the general release, so you'll need to contact Altera(field office or apps via SR) and discuss your situation. Maybe someone that has more details can chime in.Honored ContributorThank you for your replies. Suppling a .vqm file might be OK. The design is large, so reverse engineering it wouldn't be cost effective for anyone. As long as the vqm hides the RTL view, should be OK.
Bob
