IO speed limit while implementing high resolution PWM on Cyclone 10

I would like to implement high resolution PWM on a Cyclone 10 LP.

One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ended IOs (3.3V LVTTL for example) cannot switch that fast, when I compiled the design I got a [limit due to minimum port rate restriction (tmin)] with original Fmax=425MHz restricted to 223MHz. But for my application I know I can control the minimum pulse width in software. So my question is where does the IO speed limit actually apply? Does it apply in the IO buffer or does it apply in the double data rate register? In the former case that should not create a problem because I am not switching every cycle, I only want to tune the pulse width with fine steps. In the later case it would. I want to ask this for both input and output, as I might want to measure the realized switching pattern as well. 

I am aware that another possible way is to add a delay to the IO. However correct me if I am wrong, I don't see how I can dynamically choose the IO delay in any of the IP / primitives. You can dynamically change the phase of the PLL I guess, but I am not sure how fast does it stabilize at the new phase. Also If I use multiple output in my design then I would need a dedicated clock output for each output.