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linhz0hz's avatar
linhz0hz
Icon for New Contributor rankNew Contributor
7 months ago

IO speed limit while implementing high resolution PWM on Cyclone 10

I would like to implement high resolution PWM on a Cyclone 10 LP. One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ende...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
7 months ago

Hi,

timing analysis doesn't know about the actual waveform you are generating DDR output, there should be no problem for HR PWM. Minimal pulse width can be an issue, but typically it's limited by connected gate driver rather than IO standard.

Rearding dynamic phase shift feature, there's no stabilization time as long as you only manipulate output phase (C counter). Maximal variation speed is about 1 phasestep/50 ns per PLL.

Regards
Frank

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hello,


Thanks, Frank, for the answer provided. 

 

If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

Best regards,
Altera Technical Support