New Contributor
Super ContributorHi,
timing analysis doesn't know about the actual waveform you are generating DDR output, there should be no problem for HR PWM. Minimal pulse width can be an issue, but typically it's limited by connected gate driver rather than IO standard.
Rearding dynamic phase shift feature, there's no stabilization time as long as you only manipulate output phase (C counter). Maximal variation speed is about 1 phasestep/50 ns per PLL.
Regards
Frank
New ContributorThanks for the response. It seems fine for single ended output, I got issue in timing analysis but the entire compilation finished nevertheless. However if I use differential signaling (for example lvds) I got
Error (176060): The transmitter driving I/O pin pwm_out at data rate 800 Mbps exceeds the maximum allowed data rate of 640 Mbps for LVDS output
In the fitter stage and cannot finish the compilation. As I said I am oversampling the signal so the actual switching rate is much lower. Is there a way to suppress this and keep compilation going?
Thanks
Regular ContributorNo, unfortunately, you can't suppress the fitter error in Quartus. The fitter enforces a device's physical limit for LVDS outputs (e.g., 640 Mb/s). I guess that the error indicates a physical capability check of the I/O standard and is not a timing-only warning that can be silenced.
Hence, if signal integrity and board routing allow, switch the pin I/O standard to a single‑ended standard (e.g., LVTTL/3.3V) so the fitter won’t apply the LVDS hard limit. You have already seen that this compiles (with timing warnings).
Regular ContributorHello,
Thanks, Frank, for the answer provided.
If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.
Best regards,
Altera Technical Support
