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linhz0hz's avatar
linhz0hz
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10 days ago

IO speed limit while implementing high resolution PWM on Cyclone 10

I would like to implement high resolution PWM on a Cyclone 10 LP. One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ende...
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FvM's avatar
FvM
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10 days ago

Hi,

timing analysis doesn't know about the actual waveform you are generating DDR output, there should be no problem for HR PWM. Minimal pulse width can be an issue, but typically it's limited by connected gate driver rather than IO standard.

Rearding dynamic phase shift feature, there's no stabilization time as long as you only manipulate output phase (C counter). Maximal variation speed is about 1 phasestep/50 ns per PLL.

Regards
Frank

  • linhz0hz's avatar
    linhz0hz
    Icon for New Contributor rankNew Contributor
    2 days ago

    Thanks for the response. It seems fine for single ended output, I got issue in timing analysis but the entire compilation finished nevertheless. However if I use differential signaling (for example lvds) I got 

    Error (176060): The transmitter driving I/O pin pwm_out at data rate 800 Mbps exceeds the maximum allowed data rate of 640 Mbps for LVDS output 

    In the fitter stage and cannot finish the compilation. As I said I am oversampling the signal so the actual switching rate is much lower. Is there a way to suppress this and keep compilation going?

    Thanks 

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 days ago

    Hello,


    Thanks, Frank, for the answer provided. 

     

    If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

    Best regards,
    Altera Technical Support