Forum Discussion
Honored ContributorIO-Port switching using VHDL
Hello,
i have a VHDL-Project (Quartus II 9.1) wich has 96 Outputs. Every Output can be switched on/off by several entities. Every Entity wich can switch one or more Ports has a process like this: PROCESS (reset_I, clk_I) VARIABLE Port_unsigned : unsigned(7 DOWNTO 0); BEGIN IF reset_I = '1' THEN DIO_Set_O <= (OTHERS => '0'); DIO_Reset_O <= (OTHERS => '0'); ELSIF rising_edge(clk_I) THEN IF clear_config_I = '1' THEN DIO_Set_O <= (OTHERS => '0'); DIO_Reset_O <= (OTHERS => '0'); ELSE FOR i IN 1 TO nbr_of_Ports LOOP Port_unsigned := unsigned(Port_nbrs_I(i)); IF Port_values_I(i) = '1' THEN DIO_Set_O(CONV_INTEGER(Port_unsigned)) <= '1'; DIO_Reset_O(CONV_INTEGER(Port_unsigned)) <= '0'; ELSE DIO_Set_O(CONV_INTEGER(Port_unsigned)) <= '0'; DIO_Reset_O(CONV_INTEGER(Port_unsigned)) <= '1'; END IF; END LOOP; END IF; END IF; END PROCESS; Port_nbrs is the numer of the Port 1...96 to switch. nbr_of_IOs is 96 nbr_of_ports depends on the entity. Some entities have only on Port to switch, others have 2 or more. All the DIO_Set and DIO_Reset Outputs of all entities who have the process above are connected to a OR with 96 x# entites inputs and 96 outputs. After that they are connected to 96 Flip-Flops (SR), so that every entitiy can switch every Port on / off. Is there a better way to do the port-switching? I have to minimize the area of my design... Thanks in advance Paddy10 Replies
Altera_ForumHi,
all the ports of the entities have to be switched in on clock cycle. The requirements do not allow me to switch them sequentially. Paddy- Altera_Forum
If the timing requirements allow it, you can considerably reduce the logic effort by processing the commands from individual entities sequentially, one set/reset selection per clock cycle. If it's not suitable, n_entity * n_IO set and reset bits have to be processed fully parallel, there isn't much room for optimization.
Regarding conflicting accesses, you may want to define a priority of either set or reset. - Altera_Forum
Yes, it means every of my 96 Ports can be used for a at runtime defined function. Rxd can be given out at any of the Ports.
- Altera_Forum
It is not important where the date is comming from, the only important thing is that a internal port of a entity is given out at a port (1 of 96) wich can be defined at runtime. The user has to take care not to define the same portnumber for two entities.
- Altera_Forum
Does that mean a port could be used for Rx or Tx ?
- Altera_Forum
Edit- Changed cos of what you posted.
In that case, there shouldnt be any contention problems as the PC should handle that. - Altera_Forum
The entities all have equal rights. It is no problem if two entities want to switch the same port at the same time.
The complete system is a IO-Controller connected to a PC. The entities wich switch the ports are RS232 Modules, Motion-Controllers, PWM-Modules etc. With a setup command the PC can tell the system wich Port (for example RS232 TxD) is connected to wich of my 96 Outputs. - Altera_Forum
My Concern is that if you're switching based on a simple OR of all DIO sets, what happenes if two are on at the same time? which one gets the contended port?
- Altera_Forum
Hello,
the portnumbers are not constant. The entities do not know wich ports they have to switch at compilation time. The portnumbers are set at runtime, because they can change. Thanks Paddy - Altera_Forum
If the actual port usage of individual entities is known at compile time, the design compiler should know it to remove all unused logic. Because you didn't show the full application layout, it's not clear, if the compiler can get this information in your design. A construct as
--- Quote Start --- DIO_Set_O(CONV_INTEGER(Port_unsigned)) <= '1'; --- Quote End --- possibly blocks this optimizations.
When port_is_used() is a constant array or a function with constant output, the design compiler can remove all unpopulated bits of DIO_Set_O for the respective entity.FOR P IN 1 TO 96 IF P = Port_unsigned AND port_is_used(P) THEN DIO_Set_O(P) <= '1'; END IF; END LOOP;
