IO-Port switching using VHDL

If the actual port usage of individual entities is known at compile time, the design compiler should know it to remove all unused logic. Because you didn't show the full application layout, it's not clear, if the compiler can get this information in your design. A construct as

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DIO_Set_O(CONV_INTEGER(Port_unsigned)) <= '1';

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possibly blocks this optimizations.

FOR P IN 1 TO 96
  IF P = Port_unsigned AND port_is_used(P) THEN
    DIO_Set_O(P) <= '1';
  END IF;
END LOOP;

When port_is_used() is a constant array or a function with constant output, the design compiler can remove all unpopulated bits of DIO_Set_O for the respective entity.