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Honored Contributor
Honored ContributorIO-Port switching using VHDL
Hello, i have a VHDL-Project (Quartus II 9.1) wich has 96 Outputs. Every Output can be switched on/off by several entities. Every Entity wich can switch one or more Ports has a process like thi...
Altera_ForumHonored Contributor
Honored ContributorIf the timing requirements allow it, you can considerably reduce the logic effort by processing the commands from individual entities sequentially, one set/reset selection per clock cycle. If it's not suitable, n_entity * n_IO set and reset bits have to be processed fully parallel, there isn't much room for optimization.
Regarding conflicting accesses, you may want to define a priority of either set or reset.
