interfacing fft megacore ip with nios processor

i need to interface altera's fft ip core with nios processor.fft core is implementing 16k fft.To interface this fft core with scatter gather dma i made following 'manipulation' of fft core.

what i have done is grouping imaginary and real parts and exponent output is made 32 bits with eop, sop......... for it is derived seperately.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library altera;

use altera.altera_primitives_components.all;

entity newfft is

PORT (

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

inverse : IN STD_LOGIC;

sink_valid : IN STD_LOGIC;

sink_sop : IN STD_LOGIC;

sink_eop : IN STD_LOGIC;

sink_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

source_ready1 : IN STD_LOGIC;

sink_ready1 : OUT STD_LOGIC;

sink_ready2: OUT STD_LOGIC;

source_error1 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

source_error2 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

source_sop1 : OUT STD_LOGIC;

source_sop2 : OUT STD_LOGIC;

source_eop1 : OUT STD_LOGIC;

source_eop2 : OUT STD_LOGIC;

source_valid1 : OUT STD_LOGIC;

source_valid2 : OUT STD_LOGIC;

source_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

source_data2 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

end newfft;

architecture trial of newfft is

signal s1,s2,s4,s5:std_logic_vector(15 downto 0);

signal s7:std_logic_vector(31 downto 0);

signal s3:std_logic_vector(5 downto 0);

signal data1,data2,data3,data4,data5,data6:std_logic;

signal data7:std_logic_vector(1 downto 0);

component fftcore IS

PORT (

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

inverse : IN STD_LOGIC;

sink_valid : IN STD_LOGIC;

sink_sop : IN STD_LOGIC;

sink_eop : IN STD_LOGIC;

sink_real : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_imag : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

source_ready : IN STD_LOGIC;

sink_ready : OUT STD_LOGIC;

source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

source_sop : OUT STD_LOGIC;

source_eop : OUT STD_LOGIC;

source_valid : OUT STD_LOGIC;

source_exp : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);

source_real : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

source_imag : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END component fftcore;

begin

fft1:fftagain port map(clk,reset_n,inverse,sink_valid,sink_sop,sink_eop,sink_data(31 downto 16),sink_data(15 downto 0),sink_error,source_ready1,data1,data7,data2,data3,data4,s3,source_data(31 downto 16),source_data(15 downto 0));

source_sop1<=data2;

source_sop2<=data2;

sink_ready1<=data1;

sink_ready2<=data1;

source_error1<=data7;

source_error2<=data7;

source_eop1<=data3;

source_eop2<=data3;

source_valid1<=data4;

source_valid2<=data4;

source_data2(31 downto 6)<=(others=>'0');

source_data2(5 downto 0)<=s3;

end trial;

but now the problem is sgdma has an empty signal of 2 bits but fft core has got none.what to do now???

Is there any other method??