Forum Discussion

Honored Contributor

12 years ago

interfacing fft megacore ip with nios processor

i need to interface altera's fft ip core with nios processor.fft core is implementing 16k fft.To interface this fft core with scatter gather dma i made following 'manipulation' of fft core. wha...

Altera_Forum

Honored Contributor

12 years ago

Since in your other posts you've already said you've read all the documentation and don't want to be told to read it, I feel bad for saying it, but you need to read the documentation.

In particular, see:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (Section 5.3, at least)

http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf (pages 9-24 to 9-28 for starters).

Good luck!

Forum Discussion

interfacing fft megacore ip with nios processor

Recent Discussions

Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information