Occasional Contributorinterface resulting in error during synthesis
I have an interface - test_int.sv
this is used as a port in another module as shown below. it is declared as an array of 2 as i need two instances of this interfaces.
both files are added to the qsf file - test_int.sv is listed before test_module. so that interface compiles before the module where it is used.
I am using quartus 23.1
code simulates fine. but when i try to synthesize i get an error-
Do I have to declare the interface in any other place?
What am I doing wrong?
Error(17146): Verilog HDL error at test_module.sv(4): test_int is an unknown type
qsf entries
set_global_assignment -name SYSTEMVERILOG_FILE ../proj/test_int.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../proj/test_module.sv
interface test_int;
logic [63:0] signal_1;
logic [63:0] signal_2;
logic [63:0] signal_3;
modport source(
output signal_1 ,
output signal_2
);
modport destination(
input signal_3
);
endinterface
module test_module(
input data,
input cll,
test_int test_int_port[1:0]
);
endmodule
