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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

interface resulting in error during synthesis

I have an interface - test_int.sv

this is used as a port in another module as shown below. it is declared as an array of 2 as i need two instances of this interfaces.

both files are added to the qsf file - test_int.sv is listed before test_module. so that interface compiles before the module where it is used.

I am using quartus 23.1

code simulates fine. but when i try to synthesize i get an error-

Do I have to declare the interface in any other place?

What am I doing wrong?

Error(17146): Verilog HDL error at test_module.sv(4): test_int is an unknown type

qsf entries

set_global_assignment -name SYSTEMVERILOG_FILE ../proj/test_int.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../proj/test_module.sv

interface test_int;

logic [63:0] signal_1;
logic [63:0] signal_2;
logic [63:0] signal_3;


modport source(
output signal_1 ,
output signal_2
);

modport destination(
input signal_3
);

endinterface

module test_module(
input data,
input cll,
test_int test_int_port[1:0]
);
endmodule

Configuration

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    The order in the .qsf doesn't matter. I think each of your modport commands must include all 3 signals and your instantiation of test_int is incorrect. You need to create an interface object and then in the instantiation of that object, use that object and point to one of the modports. Check this out: https://www.chipverify.com/systemverilog/systemverilog-interface

    I'm not sure why this would simulate OK, but synthesis is, of course, stricter than simulation.

  • CosmoKramer's avatar
    CosmoKramer
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    thank you for replying.

    I am using interface instance in my port list so that is the first place i am using it.

    This is from the link you provided:

    All the signals do not have to be part of all the modports in the interface. Is this a Quartus requirement?

    From my understanding, we can use modports to restrict access to signals by not including them in modport.

    https://www.asic-world.com/systemverilog/interface5.html

    but to try it, i added all the signals to every modport like you suggested and i am still getting same error.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I'm not sure that you can instantiate an interface like that since you still need to reference a modport somehow to set the directions of the signals.

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