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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

interface resulting in error during synthesis

I have an interface - test_int.sv this is used as a port in another module as shown below. it is declared as an array of 2 as i need two instances of this interfaces. both files are added to the ...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

The order in the .qsf doesn't matter. I think each of your modport commands must include all 3 signals and your instantiation of test_int is incorrect. You need to create an interface object and then in the instantiation of that object, use that object and point to one of the modports. Check this out: https://www.chipverify.com/systemverilog/systemverilog-interface

I'm not sure why this would simulate OK, but synthesis is, of course, stricter than simulation.