interface resulting in error during synthesis

The order in the .qsf doesn't matter. I think each of your modport commands must include all 3 signals and your instantiation of test_int is incorrect. You need to create an interface object and then in the instantiation of that object, use that object and point to one of the modports. Check this out: https://www.chipverify.com/systemverilog/systemverilog-interface

I'm not sure why this would simulate OK, but synthesis is, of course, stricter than simulation.