interface resulting in error during synthesis

thank you for replying.

I am using interface instance in my port list so that is the first place i am using it.

This is from the link you provided:

All the signals do not have to be part of all the modports in the interface. Is this a Quartus requirement?

From my understanding, we can use modports to restrict access to signals by not including them in modport.

https://www.asic-world.com/systemverilog/interface5.html

but to try it, i added all the signals to every modport like you suggested and i am still getting same error.