interface a module with avalon bus

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Hello rromano001;

well i want to use a simple adder that i give it 2 numbers nd it calculates the sum; but i wanna use it in a Qsys system for example i will not send this calculus to the processor but i will send it to this adder nd it gives me directly the result that the processor can use it

iam new learner in that reason iam facing this difficulties

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don't worry about, I am also a quite beginner on QSYS, I learn't how to produce modules and interface but a lot has to be grasped about for parametrization, give it time and patience and you arrive wherever. For a simple adder it is not a problem to guide you but all is necessary is to understand what is your goal.

This case you need register to load operand, output of adder don't require a register due it is static computed from input.

Is not better to have a readable and writeable register on how you can do first QSYS module then customize using adder?

How much are you proficient in VHDL?

Have you experience on processor buses?

On Avalon, did you understand how Memory mapped master and slave work?

signal are presented on QSYS when you build the interface and some also have explanation.

Was of some help the guide I proposed?

On all question just add detail and on my free time I try guide/help on topic.

try google this "altera qsys reg32 component"

select "Making Qsys Components Tutorial" try follow instruction on how to create register, then when you are ready and you are able to read write register just extend using two address bit, register this case was using byte selector signals to select which byte to write, leave this and add more than one register, write read on decoded addresses 0, 1, then feed data to adder and insert another address to read adder result.

Try suggested material after that ask more help. Generate a module is not a complex task, inserting parameter is a scripting question but just start from basic module then extend it.

Actually I ported about 30 of my library module to Qsys streaming, pure conduit and memory mapped master slave devices, it is quite simple and save tedious task of writing glue top level VHDL interface connecting them.

this is the code iam trying to use

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

ENTITY adder_avalon_interface IS

PORT (

--clocks and resets

clock, resetn : IN STD_LOGIC;

--Avalon MM slave port (for nios)

avs_s0_read : IN STD_LOGIC;

avs_s0_write : IN STD_LOGIC;

avs_S0_cs : IN STD_LOGIC;

avs_s0_writedata: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

avs_s0_readdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

avs_s0_address : IN STD_LOGIC_VECTOR(1 DOWNTO 0) );

END adder_avalon_interface;

ARCHITECTURE Structure OF adder_avalon_interface IS

SIGNAL to_adder, from_adder : STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT adder

PORT ( clock, resetn : IN STD_LOGIC;

A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

C : OUT STD_LOGIC );

END COMPONENT;

BEGIN

to_adder <= writedata;

--WITH (chipselect AND write) SELECT

adder_instance: adder PORT MAP (clock, resetn, to_adder, from_adder);

readdata <= from_adder;

END Structure;

For the adder here is the code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity ADDER is

generic(n: natural :=8);

port( A: in std_logic_vector(n-1 downto 0);

B: in std_logic_vector(n-1 downto 0);

clock, resetn: in std_logic;

carry: out std_logic;

sum: out std_logic_vector(n-1 downto 0)

);

end ADDER;

architecture behavioral of ADDER is

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

process

begin

-- the 9th bit should be carry

WAIT UNTIL clock'EVENT AND clock = '1';

if resetn = '0'THEN

result <= "000000000";

else

result <= ('0' & A)+('0' & B );

end if;

end process;

sum <= result(n-1 downto 0);

carry <= result(n);

end behavioral;

yhanks for advance

Hello rromano001;

well i want to use a simple adder that i give it 2 numbers nd it calculates the sum; but i wanna use it in a Qsys system for example i will not send this calculus to the processor but i will send it to this adder nd it gives me directly the result that the processor can use it

iam new learner in that reason iam facing this difficulties

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Good evening Galfonz,

i am new in Qsys and Quartus, so can you please help me and give me an example as demonstration on how to use your suggestion of address ( plz if you can send me a code similar to this).

Thank you so much

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Hi Sarahmed, we still don't know how is made your adder, have you register? Please can you post code so we see both adder logic and interface you plan to use?

For what are you planning to use this adder? Is processor on QSYS too?

To learn try this step by step tutorial

http://www.badprog.com/electronics-quartus-ii-creating-your-first-sopc-with-qsys-and-nios-ii-software

and some hint from here

http://www.alteraforum.com/forum/showthread.php?t=40210

TO have example you need give us at almost an approximate idea of what you think build around adder, then we can guide you.

Regards

Good evening Galfonz,

i am new in Qsys and Quartus, so can you please help me and give me an example as demonstration on how to use your suggestion of address ( plz if you can send me a code similar to this).

Thank you so much

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Thank you so much Galfonz

iam new learner, and iam trying to interface an adder with avalon bus in Qsys.

i wrote a VHDL code for the adder, and i added another vhdl module to create an interface_avalon (i added the following interfaces: CLK, reset, write, writedata, readdata, chip select and external port). But, the adder has 2 inputs and 2 out put, how can i add two datawrite and dataread(it is allowed to add just one) to connect them to the 2 inputs and outputs of the adder

thanks again

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A simple adder has no sense on AValon other than using conduit for a special interface.

Adder is registered and require clock or is just a basic combinational adder?

Please can you post your code to see how it is interfaced from top level?

Thank you so much Galfonz

iam new learner, and iam trying to interface an adder with avalon bus in Qsys.

i wrote a VHDL code for the adder, and i added another vhdl module to create an interface_avalon (i added the following interfaces: CLK, reset, write, writedata, readdata, chip select and external port). But, the adder has 2 inputs and 2 out put, how can i add two datawrite and dataread(it is allowed to add just one) to connect them to the 2 inputs and outputs of the adder

thanks again

Thank you so much ted

i wonder if you can give me some advice to implement a" Direct Access Memory " with qsys

so sorry for that but iam new learner