interface a module with avalon bus

this is the code iam trying to use

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

ENTITY adder_avalon_interface IS

PORT (

--clocks and resets

clock, resetn : IN STD_LOGIC;

--Avalon MM slave port (for nios)

avs_s0_read : IN STD_LOGIC;

avs_s0_write : IN STD_LOGIC;

avs_S0_cs : IN STD_LOGIC;

avs_s0_writedata: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

avs_s0_readdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

avs_s0_address : IN STD_LOGIC_VECTOR(1 DOWNTO 0) );

END adder_avalon_interface;

ARCHITECTURE Structure OF adder_avalon_interface IS

SIGNAL to_adder, from_adder : STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT adder

PORT ( clock, resetn : IN STD_LOGIC;

A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

C : OUT STD_LOGIC );

END COMPONENT;

BEGIN

to_adder <= writedata;

--WITH (chipselect AND write) SELECT

adder_instance: adder PORT MAP (clock, resetn, to_adder, from_adder);

readdata <= from_adder;

END Structure;

For the adder here is the code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity ADDER is

generic(n: natural :=8);

port( A: in std_logic_vector(n-1 downto 0);

B: in std_logic_vector(n-1 downto 0);

clock, resetn: in std_logic;

carry: out std_logic;

sum: out std_logic_vector(n-1 downto 0)

);

end ADDER;

architecture behavioral of ADDER is

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

process

begin

-- the 9th bit should be carry

WAIT UNTIL clock'EVENT AND clock = '1';

if resetn = '0'THEN

result <= "000000000";

else

result <= ('0' & A)+('0' & B );

end if;

end process;

sum <= result(n-1 downto 0);

carry <= result(n);

end behavioral;

yhanks for advance