interface a module with avalon bus

--- Quote Start ---

Hello rromano001;

well i want to use a simple adder that i give it 2 numbers nd it calculates the sum; but i wanna use it in a Qsys system for example i will not send this calculus to the processor but i will send it to this adder nd it gives me directly the result that the processor can use it

iam new learner in that reason iam facing this difficulties

--- Quote End ---

don't worry about, I am also a quite beginner on QSYS, I learn't how to produce modules and interface but a lot has to be grasped about for parametrization, give it time and patience and you arrive wherever. For a simple adder it is not a problem to guide you but all is necessary is to understand what is your goal.

This case you need register to load operand, output of adder don't require a register due it is static computed from input.

Is not better to have a readable and writeable register on how you can do first QSYS module then customize using adder?

How much are you proficient in VHDL?

Have you experience on processor buses?

On Avalon, did you understand how Memory mapped master and slave work?

signal are presented on QSYS when you build the interface and some also have explanation.

Was of some help the guide I proposed?

On all question just add detail and on my free time I try guide/help on topic.

try google this "altera qsys reg32 component"

select "Making Qsys Components Tutorial" try follow instruction on how to create register, then when you are ready and you are able to read write register just extend using two address bit, register this case was using byte selector signals to select which byte to write, leave this and add more than one register, write read on decoded addresses 0, 1, then feed data to adder and insert another address to read adder result.

Try suggested material after that ask more help. Generate a module is not a complex task, inserting parameter is a scripting question but just start from basic module then extend it.

Actually I ported about 30 of my library module to Qsys streaming, pure conduit and memory mapped master slave devices, it is quite simple and save tedious task of writing glue top level VHDL interface connecting them.