Forum Discussion
3 Replies
- Avinash_B_P
New Contributor
DQ (data) lines are failing with setup and hold time at slow swing at read cycle. write cycle is good.
- yoichiK_altera
Contributor
Hello
Timing analysis will be analyzed in the Quartus Timing Analysis. There is DDR report tab in the Timing Analysis. User only need to check the Signal Integrity of each signals by SI simulation.
- Esteban_D_Intel
New Contributor
Hello Avinash_B_P,
Thank you for posting on the Intel® communities.
Based on your product Intel® Cyclone® 10 GX,
We would like to inform you that we have a forum for those specific issues and products, so we are moving it to the appropriate support so you can get answered more quickly.
https://community.intel.com/t5/Programmable-Devices/bd-p/programmable-devices
Esteban D.
Intel Technical Support Technician