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Avinash_B_P's avatar
Avinash_B_P
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5 years ago

Intel Cyclone 10 GX EMIF IP timing model required for DDR3 SI simulation

Hello I am running the ddrx simulation wizard with hyperlynx tool. i am DQ (data) lines are failing with setup and hold time at slow swing. for this error i wanted to run the wizard with adding tim...
Avinash_B_P's avatar
Avinash_B_P
Icon for New Contributor rankNew Contributor
5 years ago

DQ (data) lines are failing with setup and hold time at slow swing at read cycle. write cycle is good.

  • yoichiK_altera's avatar
    yoichiK_altera
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    5 years ago

    Hello

    Timing analysis will be analyzed in the Quartus Timing Analysis. There is DDR report tab in the Timing Analysis. User only need to check the Signal Integrity of each signals by SI simulation.