Instantiating Arria ii half-dsp block

Quartus should be able to automatically infer them from VHDL.

Follow the HDL coding guidelines.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Hi - thanks for the info.

I've looked thru the templates, and they all seem pointed at a particular sub-function of the block, i.e. a muliplier, a multiply add or multiply-acc function.

None of them seem to expose the chain_in/chain_out feature that I need for cascading half-dsp blocks for a FIR filter. This is shown in the Arria ii handbook in figure 4.5 - the half-dsp block diagram.

How can I get a VHDL template that corresponds to figure 4.5? Without a template it seems like I will need to attempt to model the half-dsp block in VHDL and modify it until the Quartus synth tool agrees that all the functionality can be placed in a single half-dsp block. This can be very time consuming.

THanks,

Just to be clear:

In general, there's no need to deal with the specifics of the DSP blocks.

Quartus will take multiply/multiply-add/barrel shifts operations of arbitrary widths from plain VHDL code and map them to DSP blocks, chaining as many of them as needed.

Just make sure your code is recognized by Quartus and describes behavior that can be implemented in the DSP templates.

If that doesn't work for you.. then the only way is to deal with somewhat undocumented FGPA specific primitives.

For that, you need to compile some code that makes use of DSP blocks and then look at the .vho/.vo files Quartus produces for gate level simulation to get an idea.

Note that even at that level, there isn't a 1:1 mapping between the primitives and the hardware description from the manual.

Also, take a look at the Advanced Synthesis Cookbook -- it's intended for old Stratix but it's a start.