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Honored Contributor
Honored ContributorInput Clock Multiplexer for PLL (CIII)
Hi,
I am have the following problem: I get three separate clock into my CIII FPGA (on dedicated clock inputs) and I need to choose one of the three and apply it to a PLL to frequency multiplication. Only one of the clocks are active at a time. My initial idea was to pass the clocks through a multiplexer, then through a GCLK driver and then to the PLL, but according to the databook, an internal logic signal cannot be applied to the PLL input (although from the info in the databook I cannot see why not - the PLL can be driven from a ClkCtrl output and the ClkCtrl output can be driven from an internal logic signal, but, in any case, it does not work). My second idea was to use the input multiplexer in the ClkCtrl block, thus avoiding user logic. Again, from the CIII databook (especially in figure 5-1, 5-2 and 5-4) thus seems possible. In all of these diagrams, a multipexer which seems capable of accepting up to 4 input pins, precede the PLL. Unfortunately, this seems to be misleading since the user guide for the AltClkCtrl megafunction, contains another image (Figure 1-1) which seems to indicate that the only user selectable inputs are two Clkp pins and two PLL outputs (although the figure is stated as being for the Stratix II). There seems to be little clear information on how the CIII ClkCtrl input structure looks like and what the restrictions are. Does anybody have any ideas on how I can implement such a clock multiplexer on a Cyclone III? Regards, Niki
