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Altera_Forum
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15 years ago

Input Clock Multiplexer for PLL (CIII)

Hi, I am have the following problem: I get three separate clock into my CIII FPGA (on dedicated clock inputs) and I need to choose one of the three and apply it to a PLL to frequency multiplic...
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Altera_Forum
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14 years ago

Hi Pletz,

Sorry for disturbing you again. When I try to open the project in Quartus 9.0sp2, I get the warning of version incompatibility. After that I get the same error as I had previously mentioned. If you don't mind, can you please save that project in an older version.

Actually I want to be able to perform clock division and multiplexing in Cyclone-I EP1C12 FPGA. Yesterday I had posted a thread with this issue:

http://www.alteraforum.com/forum/showthread.php?t=28536

Can you please respond to my query.

regards,

rajesh