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Altera_Forum
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15 years ago

Input Clock Multiplexer for PLL (CIII)

Hi, I am have the following problem: I get three separate clock into my CIII FPGA (on dedicated clock inputs) and I need to choose one of the three and apply it to a PLL to frequency multiplic...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi Kevin / Pletz,

Thanks for the response! I also figured out the solution proposed by Kevin. To address the increased jitter problem of having two PLLs cascaded I tried to just mux the outputs of the two PLLs through a 2:1 mux in user logic and then drive it back onto a global clock. This seems to work, but I guess I use an extra Clock Control Block.

Pity there are so many constraints on the use of the clock control blocks and the routing of clocks. But I guess it is tricky to make it more generic.

Regards,

Niki