Forum Discussion
Honored ContributorIncrease data rate
In my design, there are 8-bit parallel data output from the FPGA. I don't have a problem with its TimeQuest analysis. However, the setup slacks for the 8-bits with respect to the clock are very different. The max difference between the max setup slack and the min setup slack is about 1.8ns. I wonder if anybody knows how to reduce the difference and thus increase data rate. By the way, the Altera mysupport suggested using set_max_delay and set_min_delay. After I tried a few options, there was a very little or no improvement.
Many thanks.4 Replies
Altera_ForumHi Guys,
Thank you very much indeed for your replies. 1. I did use "Fast Output Registers". 2. The setup slacks are all positive. 3. The longest delays are caused by IOOBUF delays. 4. I think that the timing difference of data matters. The big the timing difference is, the slower the data rate will be. 5. I did use one VREF pins for the data. After I moved the data bit to a non-VREF pin, there is a significant improvement. Now the max time difference among the data bits is less than 0.3ns. I really appreciate your suggestions. Many thanks and best regards, Bcao- Altera_Forum
Also, if you used any VREF pins as regular IO they have an extra delay associated with them.
- Altera_Forum
Is that 1.8ns across timing models or within a single timing model. As josyb said, if the outputs are registered then the difference within a model should be very small. Also, is the slack positive or negative? If it's all positive, then it's all passing timing and that difference doesn't matter. I'm assuming it's negative, which means the fitter is working on it. You might want to analyze two paths and see why they're different and why they can't be made better.
- Altera_Forum
Assuming that the output port is registered: add a "Fast Output Register" for the port in the assignment editor.
