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Altera_Forum's avatar
Altera_Forum
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16 years ago

Increase data rate

In my design, there are 8-bit parallel data output from the FPGA. I don't have a problem with its TimeQuest analysis. However, the setup slacks for the 8-bits with respect to the clock are very diffe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Is that 1.8ns across timing models or within a single timing model. As josyb said, if the outputs are registered then the difference within a model should be very small. Also, is the slack positive or negative? If it's all positive, then it's all passing timing and that difference doesn't matter. I'm assuming it's negative, which means the fitter is working on it. You might want to analyze two paths and see why they're different and why they can't be made better.