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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Increase data rate

In my design, there are 8-bit parallel data output from the FPGA. I don't have a problem with its TimeQuest analysis. However, the setup slacks for the 8-bits with respect to the clock are very diffe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Assuming that the output port is registered: add a "Fast Output Register" for the port in the assignment editor.