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Altera_Forum's avatar
Altera_Forum
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15 years ago

Increase data rate

In my design, there are 8-bit parallel data output from the FPGA. I don't have a problem with its TimeQuest analysis. However, the setup slacks for the 8-bits with respect to the clock are very diffe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Guys,

Thank you very much indeed for your replies.

1. I did use "Fast Output Registers".

2. The setup slacks are all positive.

3. The longest delays are caused by IOOBUF delays.

4. I think that the timing difference of data matters. The big the timing difference is, the slower the data rate will be.

5. I did use one VREF pins for the data. After I moved the data bit to a non-VREF pin, there is a significant improvement. Now the max time difference among the data bits is less than 0.3ns.

I really appreciate your suggestions.

Many thanks and best regards,

Bcao