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Altera_Forum
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17 years ago

Implementing an accumulator and data recovery system

Hi,

I'm struggling to implement an accumulator or an equivalent system using VHDL. I require it as part of my receiver design at add 26 bits and tell me whether the result was positive of negative. my processes use signed 2's complement representation. here is the code that i have made thus far.

-----------------------------------------------

--23/10/08 Accumulator design

--this block is supposed to add all the bits coming into the input

--and then send the output to the decision device

--quartus does not recognise the "+" operator:confused:?????

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_signed.all;

use ieee.numeric_bit.all;

entity accum is

port(clk : in std_logic;

data_in : in std_logic_vector (25 downto 0);

ready : in std_logic;

trigger : out std_logic;

data_out : out std_logic_vector (4 downto 0)--5 bit ouput

);

end accum;

architecture dt1 of accum is

begin

process(clk)

variable temp : std_logic_vector (25 downto 0);

begin

if rising_edge(clk) then

if ready='1' then

temp:= data_in;

data_out <= (temp(0) + temp(1) + temp(2) + temp(3) + temp(4) + temp(5)

+ temp(6) + temp(7) + temp(8) + temp(9) + temp(10) + temp(11)

+ temp(12) + temp(13) + temp(14) + temp(15) + temp(16) + temp(17)

+ temp(18) + temp(19) + temp(20) + temp(21) + temp(22) + temp(23)+

temp(24) + temp(25)); --adding all the parallel data

trigger<='1';

else trigger <='0';

end if;

end if;

end process;

end dt1;

----------------------------------------

Below is a decription of the recovery scheme i'm trying to implement

-------------------------------------

data at the receiver arrives as 14 signed bits then its multiplied by 2-bit walsh code resulting in 16-bits, this result is multiplied by 10-bit wavelet, the result is then sent at a summer and decision device

--received data (14-bits)--->(x)walsh code(2-bits)------>(x)wavelet(10-bits)------->Accumulator(sum of elements)------->Decision device----->recovered data(binary)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi Zadok

    For addition I suggest that you convert a single bit to unsigned bus(one bit or if Quartus not happy two bits) then add all your data. However, your adder chain is very long and you are likely to have timing problem. If so, consider pipelining.

    Kaz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hi there,

    i'm trying to implement a ROM in software using the code below, it works but i get some phanton data between the actual data that i am sending out when i simulate it using the waveform editor.

    --11/10/08 Second vesion of the rom, this time using the clock to directly cycle out the data

    --this version will not use the case statement, but use an if loop, a counter to cycle out the data at a

    --particular frequency.

    --based on code obtained form a help site http://www.edaboard.com/forum75.html

    --and wikivesity, an article on Computer Architecture Lab/HOWTO visited 27/09/08

    --21/10/08 Version two changed to add a ready signal

    --24/10/08--edited to add a trigger line and to add ready to the sensitivity list

    --29th/10/08--edited to ensure the last rom position is sent out. to do this i increased the count value

    library ieee;

    use ieee.std_logic_1164.all;

    entity prbs is

    port(r_clk : in std_logic;--clock input at the user data frequency

    ready : in std_logic;--ready signal from sync

    trigger : out std_logic;

    r_data : out std_logic_vector (9 downto 0);--wavelet data vector representing a portion of the wavelet

    counter : out integer

    );

    end prbs;

    architecture prbs of prbs is

    type mem is array (0 TO 9) of std_logic_vector (9 downto 0);

    constant rom : mem :=(

    0 => "0000000100",

    1 => "0000000111",

    2 => "1111101011",

    3 => "0000011100",

    4 => "1110110100",

    5 => "1111101011",

    6 => "0011000011",

    7 => "1110110100",

    8 => "1110011000",

    9 => "0000111011"

    );

    begin

    process(ready,r_clk)

    variable count : integer :=0;--defining a counter

    begin

    if ready='1' then

    if rising_edge(r_clk) then--i'm not sure whether the program will return here after sending out the data!

    r_data<=rom(count);

    counter<=count;

    count:=count+1;

    if count=11 then --check whether the ROM addresses have been exceeded

    count:=0;

    trigger<='1';--trigger next module

    else trigger<='0';

    end if;

    end if;

    end if;

    end process;

    end prbs;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    try this process(I didn't test the code, expect some syntax issues)

    signal count : integer range 0 to 9;

    process(reset,r_clk) -- add reset to your module

    begin

    if reset='1' then

    count <= 0;

    trigger <= '0';

    r_data <= (others => '0');

    elsif rising_edge(r_clk) then

    if(ready = '1')then

    r_data<=rom(count);

    if(count = 9)then

    count <= 0;

    trigger <= '1';

    else

    count <= count + 1;

    trigger <= '0';

    end if;

    end if;

    end if;

    end process;

    counter <= count; -- or move this up if you need addr/data together