Implementing an accumulator and data recovery system

hi there,

i'm trying to implement a ROM in software using the code below, it works but i get some phanton data between the actual data that i am sending out when i simulate it using the waveform editor.

--11/10/08 Second vesion of the rom, this time using the clock to directly cycle out the data

--this version will not use the case statement, but use an if loop, a counter to cycle out the data at a

--particular frequency.

--based on code obtained form a help site http://www.edaboard.com/forum75.html

--and wikivesity, an article on Computer Architecture Lab/HOWTO visited 27/09/08

--21/10/08 Version two changed to add a ready signal

--24/10/08--edited to add a trigger line and to add ready to the sensitivity list

--29th/10/08--edited to ensure the last rom position is sent out. to do this i increased the count value

library ieee;

use ieee.std_logic_1164.all;

entity prbs is

port(r_clk : in std_logic;--clock input at the user data frequency

ready : in std_logic;--ready signal from sync

trigger : out std_logic;

r_data : out std_logic_vector (9 downto 0);--wavelet data vector representing a portion of the wavelet

counter : out integer

);

end prbs;

architecture prbs of prbs is

type mem is array (0 TO 9) of std_logic_vector (9 downto 0);

constant rom : mem :=(

0 => "0000000100",

1 => "0000000111",

2 => "1111101011",

3 => "0000011100",

4 => "1110110100",

5 => "1111101011",

6 => "0011000011",

7 => "1110110100",

8 => "1110011000",

9 => "0000111011"

);

begin

process(ready,r_clk)

variable count : integer :=0;--defining a counter

begin

if ready='1' then

if rising_edge(r_clk) then--i'm not sure whether the program will return here after sending out the data!

r_data<=rom(count);

counter<=count;

count:=count+1;

if count=11 then --check whether the ROM addresses have been exceeded

count:=0;

trigger<='1';--trigger next module

else trigger<='0';

end if;

end if;

end if;

end process;

end prbs;