Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Implementing an accumulator and data recovery system

Hi, I'm struggling to implement an accumulator or an equivalent system using VHDL. I require it as part of my receiver design at add 26 bits and tell me whether the result was positive of negat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

try this process(I didn't test the code, expect some syntax issues)

signal count : integer range 0 to 9;

process(reset,r_clk) -- add reset to your module

begin

if reset='1' then

count <= 0;

trigger <= '0';

r_data <= (others => '0');

elsif rising_edge(r_clk) then

if(ready = '1')then

r_data<=rom(count);

if(count = 9)then

count <= 0;

trigger <= '1';

else

count <= count + 1;

trigger <= '0';

end if;

end if;

end if;

end process;

counter <= count; -- or move this up if you need addr/data together