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Altera_Forum
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18 years ago

Implementing an accumulator and data recovery system

Hi, I'm struggling to implement an accumulator or an equivalent system using VHDL. I require it as part of my receiver design at add 26 bits and tell me whether the result was positive of negat...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi Zadok

For addition I suggest that you convert a single bit to unsigned bus(one bit or if Quartus not happy two bits) then add all your data. However, your adder chain is very long and you are likely to have timing problem. If so, consider pipelining.

Kaz