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Altera_Forum's avatar
Altera_Forum
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8 years ago

Implementation of VHDL program on FPGA

Hello,

I try to implement a simple vhdl program " if the switch button is ON then the led has to be ON" on FPGA using Quartus but it doesn't work means the switch is ON but the led is still OFF. however, when i implement a block diagram using quartus on FPGA it works !!!. Is there an option which have to be activated on the tools? how can i solve the problem ?

Many thanks

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Its probably an issue in the code/project

    why not post the code/project?
  • Altera_Forum's avatar
    Altera_Forum
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    Here is the code :

    library ieee;

    use ieee.std_logic_1164.all;

    use IEEE.STD_LOGIC_ARITH.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity TEST is port (

    bouton: in std_logic;

    led0: out std_logic ;

    led1: out std_logic ;

    led2: out std_logic ;

    led3: out std_logic

    );

    end TEST;

    architecture behavior of TEST is

    begin

    process (bouton)

    begin

    if bouton = '1' then

    led0 <= '0';

    led1 <= '1';

    led2 <= '1';

    led3 <= '1';

    nd if;

    end process;

    end behavior;
  • Altera_Forum's avatar
    Altera_Forum
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    You forgot the else to change the state of the leds when the button is in the off state.

  • Altera_Forum's avatar
    Altera_Forum
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    Even with the else it doesnt work.. :(.is there an option which has to be activated on quartus to indicate the type of the transfered program to fpga ?

  • Altera_Forum's avatar
    Altera_Forum
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    have you included the code in the project? have you got a correct pinout?

    is the code even correct - why not post it rather than just say "it doesnt work".
  • Altera_Forum's avatar
    Altera_Forum
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    yes i have the correct pinout.

    library ieee;

    use ieee.std_logic_1164.all;

    use IEEE.STD_LOGIC_ARITH.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity TEST is port (

    bouton: in std_logic;

    led0: out std_logic ;

    led1: out std_logic ;

    led2: out std_logic ;

    led3: out std_logic

    );

    end TEST;

    architecture behavior of TEST is

    begin

    process (bouton)

    begin

    if bouton = '1' then

    led0 <= '0';

    led1 <= '1';

    led2 <= '1';

    led3 <= '1';

    else

    led0 <= '1';

    led1 <= '0';

    led2 <= '0';

    led3 <= '0';

    end if;

    end process;

    end behavior;
  • Altera_Forum's avatar
    Altera_Forum
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    Hi berkoka,

    I would suggest that you run a functional simulation with Modelsim with your codes prior to hardware testing. With this, we can be sure if the codes are working and isolate functional related issue prior to hardware debugging.

    Best Regards,

    bfkstimchan

    (This message was posted on behalf of Intel Corporation)