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Altera_Forum
Honored Contributor
8 years agoyes i have the correct pinout.
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TEST is port ( bouton: in std_logic; led0: out std_logic ; led1: out std_logic ; led2: out std_logic ; led3: out std_logic ); end TEST; architecture behavior of TEST is begin process (bouton) begin if bouton = '1' then led0 <= '0'; led1 <= '1'; led2 <= '1'; led3 <= '1'; else led0 <= '1'; led1 <= '0'; led2 <= '0'; led3 <= '0'; end if; end process; end behavior;