i2c problem

--- Quote Start ---

The Sda line changes the state on the scl='1'

--- Quote End ---

You mean, your code operates it this way?

--- Quote Start ---

The sda is pulled up to vdd.

--- Quote End ---

That's how I2C works. Bus drivers should operate as open drain, which is simple with a FPGA I/O pin.

--- Quote Start ---

Does altera provide any solutions for these problems?

--- Quote End ---

DE2 is a Terasic product, shipped with Verilog demonstration code. It's basically working, but not particularly instructive. The I2C related code, as far as I'm aware of is pretty basic and can be converted to VHDL without deep Verilog knowledge (in my opinion). Others have probably written own I2C code from the scratch based on the NXP specification or used IP from the internet.

--- Quote Start ---

You mean, your code operates it this way?

That's how I2C works. Bus drivers should operate as open drain, which is simple with a FPGA I/O pin.

DE2 is a Terasic product, shipped with Verilog demonstration code. It's basically working, but not particularly instructive. The I2C related code, as far as I'm aware of is pretty basic and can be converted to VHDL without deep Verilog knowledge (in my opinion). Others have probably written own I2C code from the scratch based on the NXP specification or used IP from the internet.

--- Quote End ---

No. It seems it has a delay that makes the sda to go from 'H' to 'L' in this way. My code is made from scratch ,and when i make simulations in modelsim it works, but when i implement on the bord, it acts like this.

What is NXP specification? I never heard about this. Thank you!

Philips/NXP has invented the I2C bus, their specification should be the basic document to implement a bus controller:

http://www.nxp.com/acrobat_download/usermanuals/um10204_3.pdf

Seriously, the FPGA hasn't the option to introduce a considerable delay to a pin on it's own(at least compared to the 100 or 400 kHz I2C speed). So it must be in your code.

--- Quote Start ---

Hello.

I made a i2c to configure in sidetone the audio codec on de2 bord. It seems i may encounter two problems:

1. The Sda line changes the state on the scl='1' insted of scl='0', so the i2c is in start state always.

2. The sda is pulled up to vdd. How can i transmit 0 an 1 to the audio codec?

Dose altera provide any solutions for these problems?

PS:I'm working in VHDL!

--- Quote End ---

I have encountered similar problems in SMBus(a subset of I2C) last year. I suggest you check your state machine deliberately to meet the I2C timing request.